The present invention relates to an arithmetic-logic unit (ALU), and more particularly to a parallel arithmetic-logic unit (PALU) for use in a digital signal processing (DSP) microchip which is capable of executing a conditional operation in a single pass through the PALU.
Parallel arithmetic-logic units are well known in the arts (see, e.g. ADSP-2100 User's Manual, Chapter 2.2, Analog Devices Inc., 1986). Typically they contain one or more input registers, an optional shifter, and an arithmetic-logic core. In addition they may contain one or more output registers (accumulators). The PALU's known in the art are capable of conducting many arithmetic and logical operations under the control of a microinstruction sequencer. For example, subtraction and addition of values in the registers and/or accumulators (immediate data from a MIS ROM, and data from a RAM also typically being available as a source of a value) as well as the negation, incrementing, or decrementing of a register or accumulator value may be accomplished. Likewise, logical functions such as the AND, OR or XOR of the values in the registers and/or accumulators may be accomplished by the PALU. The results of the functions (i.e. the values) which can be stored in the accumulators are then typically available for placement on a data bus for sending them to a desired location in the processor.
Those skilled in the art will recognize that the arithmetic and logical operations common to the PALU's of the art as described above are one pass operations; that is, after the related registers are loaded with desired values, a single command from the microinstruction sequencer actuates the desired operation in the PALU, and the PALU is able to accommodate and execute the command in a single cycle without repetitively using the arithmetic-logic core. However, where more complex operations such as limiting (bounding) a variable between an upper and lower limit (i.e. IF A&gt;B THEN A=B, ELSE A=A) is to be acomplished, the PALU's of the art require a two pass operation; that is, the results obtained by the operation of the arithmetic-logic core on first pieces of information are used in the conducting by the arithmetic-logic core of a second operation. For example, in the upper bounding operation, after loading an accumulator or register with a first value A, a first microinstruction would be required to have the PALU compare the first value A with a second value B (probably by subtracting B from A) and to accordingly set a flag to be read by the microinstruction sequencer. Thus, a first pass through the PALU would comprise such a comparison (subtraction). Based on the flag, the microinstruction sequencer would then branch to a desired location in its program and issue a second microinstruction to the PALU to either set A to B or A to A. In the second pass, the PALU would execute the instruction to set A to the appropriately dictated value through the use of a data move command.
The two pass requirement in the PALU for performing operations such as an IF-THEN-ELSE operation has several drawbacks. First, with a two pass arrangement, two sets of communications between the microinstruction sequencer and the PALU are required. The necessity of two sets of communications slows down the flow of the operation as the microinstruction sequencer must first send a command and then await the results of the comparison pass through the PALU before determining the next proper microinstruction. Second, with a two pass arrangement, not only is the operation slowed down, but additional MIS microinstructions are required, thereby necessitating a larger microinstruction sequencer ROM, or alternatively, thereby limiting the range of operations which will be available. Finally, where a comparison of two register values is conducted by a subtraction operation in the arithmetic-logic core, one of the values may be corrupted if a special MIS microinstruction is not provided to specifically avoid corrupting the accumulator register. Thus, yet additional microinstructions would have to be listed in the MIS, and the PALU would be forced to accommodate additional instructions.